1. Field of the Invention
The present invention relates to a semiconductor device containing an interconnection structure comprising conductive wiring on a substrate, and more particularly to a dual damascene process for forming an interconnection structure.
2. Description of the Prior Art
Normally traditional methods for forming interconnection structures conclude the use of subtractive etching or etch back step as the primary metal-patterning techniques. It was also developed as dual damascene process for a practical technique.
One such traditional technique is illustrated in part in FIGS. 1A to 1I, wherein inter-layer dielectrics layer as an oxide layer 112, such as FIG. 1A is formed on semiconductor substrate 111 that is as mono-crystalline silicon. With conductive contacts/vias 113 formed in inter-layer dielectrics layer 112 such as FIG. 1B. FIG. 1B also illustrated inter-layer dielectrics layer 114 is deposited on etching stop layer 113, such as Silicon Nitride. The interconnection structure comprises conductive contacts/vias 113 and conductive wiring 114. Then a photoresist mask 115 formed on inter-layer dielectrics layer 114 corresponding to the wiring pattern as shown FIG. 1C. After etching, as FIG. 1D, wiring line pattern is formed using lithography progress. The following step, again a photoresist layer 116 is applied to the resulting wiring pattern shown as FIG. 1E, and then the wiring pattern formed as FIG. 1F. Consequently photoresist mask is removed soon shown as FIG. 1G. Finally metal is not only deposited onto the surface of above semiconductor device but also filled up the opening as FIG. 1H. FIG. 1I shows the excess metal is removed using typically chemical mechanical polishing process.
Commonly the photoresist layer should be formed thicker for using and owning a long depth of focus in order to expose the entire thickness of the photoresist mask. However, for use of steppers that need high solution, it is difficult in forming quite deep focus in the process. Also it makes thick critical dimension happening and reduces reliability of production.
Moreover, as forming semiconductor integrated circuits devices, a first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. More interconnections are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device.